
VPSLLVD/VPSLLVQ - Variable Bit Shift Left Logical.VPERMPS - Permute Single-Precision Floating-Point Elements.VPERMPD - Permute Double-Precision Floating-Point Elements.VPERMD - Full Doublewords Element Permutation.PSUBUSB/PSUBUSW -Subtract Packed Unsigned Integers with Unsigned Saturation.PSUBSB/PSUBSW -Subtract Packed Signed Integers with Signed Saturation.PSUBB/PSUBW/PSUBD/PSUBQ -Packed Integer Subtract.PSRLW/PSRLD/PSRLQ - Shift Packed Data Right Logical.PSRAW/PSRAD - Bit Shift Arithmetic Right.PSADBW - Compute Sum of Absolute Differences.PMULUDQ - Multiply Packed Unsigned Doubleword Integers.PMULLW/PMULLD - Multiply Packed Integers and Store Low Result.PMULHW - Multiply Packed Integers and Store High Result.PMULHUW - Multiply Packed Unsigned Integers and Store High Result.
PMULHRSW - Multiply Packed Unsigned Integers with Round and Scale. PMULDQ - Multiply Packed Doubleword Integers. PHSUBSW - Packed Horizontal Subtract with Saturation. PHSUBW/PHSUBD - Packed Horizontal Subtract. PHADDSW - Packed Horizontal Add with Saturation. MPSADBW - Multiple Sum of Absolute Differences. 5.1.6 CPUID Support column in the Instruction Summary Table. 5.1.5 64/32 bit Mode Support column in the Instruction Summary Table. 5.1.4 Operand Encoding column in the Instruction Summary Table. 5.1.3 Instruction Column in the Instruction Summary Table. 5.1.2 Opcode Column in the Instruction Summary Table. 5.1 Interpreting InstructIon Reference Pages. 4.3 VEX Encoding Support for GPR Instructions. 4.2 Vector SIB (VSIB) Memory Addressing. 4.1.9.1 Vector Length Transition and Programming Considerations. 4.1.8 The Third Source Operand (Immediate Byte). 4.1.7 The MODRM, SIB, and Displacement Bytes. 4.1.5 Instruction Operand Encoding and VEX.vvvv, ModR/M. 4.1.2 VEX and the 66H, F2H, and F3H prefixes. 3.2.6 Processor Extended State Save Optimization and XSAVEOPT. 3.2.5 XSAVE/XRSTOR Interaction with YMM State and MXCSR. 3.1 YMM State, VEX Prefix and Supported Operating Modes. 2.8.3 Unaligned Memory Access and Buffer Size Management. 2.8.1 Clearing Upper YMM State Between AVX and Legacy SSE Instructions. 2.7.8 Exceptions Type 8 (AVX and no memory argument). 2.7.7 Exceptions Type 7 (No FP exceptions, no memory arg). 2.7.5 Exceptions Type 5 (<16 Byte mem arg and no FP exceptions). 2.7.3 Exceptions Type 3 (<16 Byte memory argument).
2.7.2 Exceptions Type 2 (>=16 Byte Memory Reference, Unaligned). 2.7.1 Exceptions Type 1 (Aligned memory reference). 2.7 Instruction Exception Specification. 2.3.1 FMA Instruction Operand Order and Arithmetic Behavior. 2.2 Detection of AVX and FMA Instructions. 2.1 Detection of PCLMULQDQ and AES Instructions. 1.6 General Purpose Instruction Set Enhancements. 1.3.3 VEX Prefix Instruction Encoding Support. Chapter 1 Intel® Advanced Vector Extensions.